Rugged silicon-containing surfaces are utilized in numerous semiconductor constructions. For instances, rugged silicon-containing surfaces are frequently utilized as storage nodes of capacitor constructions. The rugged surfaces can increase a surface area of the storage node, and thereby can increase the amount of capacitance per unit surface area of the storage node relative to a non-rugged surface. An exemplary form of rugged silicon is hemispherical grain (HSG) silicon.
Difficulties are encountered in controlling the roughness of a rugged silicon-containing surface. FIGS. 1-5 describe an exemplary prior art process for forming a rugged silicon-containing surface, and also describe a potential source of the difficulty in controlling roughness of the rugged surface.
Referring initially to FIG. 1, a graph 10 is provided to show the typical temperature control utilized in forming a rugged silicon surface. An amorphous silicon layer is formed over a substrate at an initial temperature T1. Such initial temperature will typically be from about 480° C. to about 520° C. The formation of the amorphous silicon corresponds to step 12 in the graph of FIG. 1.
The amorphous silicon is subsequently heated to a second temperature T2, which is typically from about 560° C. to about 620° C., and can be from about 580° C. to about 620° C. The heating of the substrate is illustrated by a ramp 14 in the graph of FIG. 1.
After the substrate reaches the temperature T2, it is exposed to silane to form seed crystals, and subsequently is annealed to form the rugged silicon-containing surface. The silane exposure and annealing both typically occur at the temperature T2, and would occur during the step 16 of FIG. 1.
Referring to FIG. 2, a semiconductor wafer construction 20 is illustrated at the processing stage 12 of the FIG. 1 graph. Specifically, construction 20 comprises a substrate 22 and a layer of amorphous silicon 24 over such substrate. Substrate 22 can comprise, for example, monocrystalline silicon. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
FIG. 3 shows the construction 20 after the temperature has been ramped in accordance with the processing stage 14 of FIG. 1. It is noted that the change in temperature has caused some flow of the amorphous silicon of layer 24, and accordingly humps 26 have formed at regions of layer 24.
FIGS. 4 and 5 illustrate construction 20 during the processing of stage 16 of FIG. 1. Specifically, FIG. 4 illustrates seeds 28 formed by exposure of layer 24 to silane, and FIG. 5 shows layer 24 after appropriate annealing to incorporate the seeds into a rugged surface 30. It is noted that the peaks 26 are significant features across the surface of layer 24 after the annealing.
A dashed line 32 is provided in FIG. 5 to approximately illustrate the base of the rugged surface of layer 24. Features associated with the rugged surface can be characterized in terms of a width at half height of such features. The height is measured relative to base 32. Accordingly, one of the features 26 is shown having a height 34. The width of such feature at half height is indicated by arrow 36. The width at half height of feature 26 would typically be very large, frequently is greater than 1000 Å, and will often even exceed 3000 Å. In contrast, a feature 40 having the primary contribution from a seed (shown as 28 in FIG. 4), rather than from a peak generated during the ramping of temperature of layer 24, will typically have a width at half height of 500 Å or less.
The large variation in feature sizes of the rugged surface of FIG. 5 can create problems in controlling the uniformity of the ruggedness of such surface. Accordingly, it would be desirable to develop new methods for forming a rugged silicon-containing surface which reduce the variation in feature size relative to the variations occurring in prior art processing.